1. Field of the Invention
The present invention relates to a CMOS image sensor, more particularly, to a CMOS image sensor and a fabrication method thereof comprising a photo diode region that is expanded over all the lower portion of an active region where a transfer gate is formed so as to enhance the sensitivity of the sensor and that has different potential level according to a position in the photo diode region.
2. Discussion of the Related Art
Recently, the functions of most electronic productions are versatile. For instance, a personal computer is equipped with a compact diskxe2x80x94read only memory (CD-ROM) driver, a digital versatile disk (DVD) player, or a camera for a video conference. Also, for editing pictures by using a computer, digital cameras attached to computers are commonly for sale. Even a notebook computer and a cellular phone having a small size camera mounted within them will be put in large quantities on a market soon.
Attaching a camera to a large size product like personal computer does not cause any troubles in using it. However, portable products of small size such as a notebook computer or a cellular phone will have serious problems in case of being attached with a camera since a typical product uses a charge coupled device as an image sensor (a photosensitive device). But the charge coupled device (CCD) consumes a large power and therefore a large cell has to be used for the camera.
Most CCD devices that have been already developed are driven by higher voltage (+15 to xe2x88x929 V) than a CMOS circuit and a fabrication process of the CCD devices are basically similar to a fabrication process of bipolar transistor. Therefore, the cost for fabricating the CCD devices is much higher than the case for the CMOS.
In order to solve a such a problem, a study on implementing and producing CMOS image sensors has been done to realize the CCD image sensors being operated by a low voltage and a low power consumption as well as having a low production cost.
A conventional CMOS image sensor will be described as follows by referring to the accompanying drawings.
FIG. 1 is a cross sectional view of 3 transistor (TR) pixel structure of a conventional CMOS image sensor and FIG. 2 is a circuit configuration of the 3 TR pixel of the conventional CMOS image sensor.
FIG. 1 shows a cross sectional view of a three transistor pixel structure of a conventional CMOS image sensor. Since a standard CMOS process is conventionally applied to a CMOS image sensor, an n type well 102 is formed in a p type semiconductor substrate 100 to form a light receiving portion.
In order to sense image charges generated in the light receiving portion, a p type well 101 is formed adjacent to said n type well 102.
A n+ region 103a is extended from the surface of the n type well 102 to a portion of the surface of the p type well 101.
The n+ region 103a is used as a channel to move the image charges. An n+ region 103b is formed in a portion of the surface of the p type well region 101 spaced apart from the n+ region 103a and is used as a floating region in which sensing operation for the image charges is performed.
Next, a transfer gate 104 for transferring the charges is formed over the substrate between the n+ region 103a and the n+ region 103b. 
FIG. 2 shows a circuit configuration of a three transistor (TR) pixel structure of a conventional CMOS image sensor. The circuit of 3 TR pixel structure is constructed with a reset transistor 1, a select transistor 4 and an access transistor 7.
The reset transistor 1 has a gate to receive a reset signal through a signal input terminal 2, one electrode connected to a floating node 5 and the other electrode connected to a VDD terminal 3. The select transistor 4 has a gate connected to the floating node 5 and one electrode connected to the VDD terminal 3. The other electrode of the select transistor 4 is connected to the access transistor 7. The access transistor 7 is connected in series between the select transistor 4 and a column select line 9. The gate of the access transistor 7 is connected to a row select signal input terminal 8 so as to receive a row select signal. A photo diode 6 is connected between said floating node 5 and a ground terminal 10.
The sensing operation of the 3 TR of the conventional CMOS image sensor is described as follows.
Image charges that are induced by incident light from outside to a photo diode 6 are accumulated in the photo diode 6. The accumulated signal charges therein change a potential of the floating node 5 which is used as a source terminal of the reset transistor 1 and therefrom change the gate potential of the select transistor 4 which is used as a driver of a pixel level source follower. The change of the gate potential of the select transistor 4 causes the bias of the node for a drain of the access transistor 7 and a source of the select transistor 4 to be changed.
Thus, while signal charges are accumulated in the photo diode 6, potentials at the sources of the reset and select transistors 1 and 4 are changed. At this time, if a row select signal is applied to the gate of the access transistor 7 through a row select signal input terminal 8, then a potential difference due to the signal charges generated in the photo diode 6 is transferred to a column select line 9.
After the signal level due to the signal charges generated in the photo diode 6 is detected, the reset transistor 1 is turned on by the reset signal received through the reset signal input terminal 2 and all the signal charges accumulated in the photo diode 6 are reset.
In order to solve the noise problem of the conventional CMOS image sensors of 3 TR pixel structure, a CMOS image sensor of 4 TR pixel structure has been studied and is described as follows.
FIG. 3 is a cross sectional diagram showing a conventional CMOS image sensor of a 4 TR pixel structure and FIG. 4 is a circuit configuration of the 4 TR pixel structure of the conventional image sensor.
As shown in FIG. 3, a p-type epitaxial layer 301 is formed on a p-type semiconductor substrate 300 and an n type well region 302 is formed in a portion of said p-type epitaxial layer 301.
In a portion of the surface of the p-type epitaxial layer 301, a photo diode region consists of an n+impurity doped layer 303 in the p-type epitaxial layer 301 and a p+surface impurity layer 307 formed on a surface of the impurity doped layer 303.
A n+ region 304 is formed in a portion of a p-type epitaxial layer 301 spaced apart from the photo diode region. The n+ region is used as a floating diffusion region for sensing image charges.
Another n+ region 309 is formed in a p type epitaxial layer 301 spaced apart from the n+ region 304 and is connected to a power supply voltage VDD.
A lightly doped n-type impurity layer 308 is formed in a surface of the p-type epitaxial layer 301 between the photo diode region 303 and 307 and the n+ region 304, and a transfer gate 305 is formed over the lightly doped n-type impurity layer 308.
Next, a reset gate 306 is formed over the surface of the epitaxial layer 301 between the n+ region 304 and the n+ region 309.
A circuit configuration and a charge sensing operation of the conventional CMOS image sensor of 4 TR pixel structure will be described as follows by referring to FIG. 4.
The circuit of 4 TR pixel structure is constructed with a reset transistor 21, a select transistor 24, an access transistor 30, a transfer transistor 29 and a photo diode 27.
The reset transistor 21 has a gate receiving a reset signal through a reset signal input terminal 22. One electrode of the reset transistor 21 is connected to a floating node 25 and the other electrode of the reset transistor 21 is connected to a VDD terminal 23. The select transistor 24 has a gate connected to the floating node 25. One electrode of the select transistor 24 is connected to the VDD terminal 23. The other electrode of the select transistor 24 is connected to the access transistor 30.
The gate of the access transistor 30 is connected to a row select signal input terminal 31 so as to receive a row select signal.
The other electrode of the access transistor 30 is connected to a column select line 32.
The transfer transistor 29 has a gate connected to a transfer signal input terminal 28. One electrode of the transfer transistor 29 is connected to the floating node 25 and the other electrode is connected to a photo diode 27. When reading the accumulated charges, the transfer transistor 29 performs an operation transferring image charges.
The photo diode 27 has the other electrode connected to a ground 10 and a photo gate 26. When transferring the charges, the photo gate 26 performs an operation collecting the accumulated charges upon the surface.
The sensing operation of the conventional CMOS image sensor of the 4 TR pixel structure will be described as follows.
First, image charges induced via incident light are accumulated in the photo diode 27.
The accumulated signal charges are collected on the surface of the photo diode 27 when the bias of the photo gate 26 is changed to a high level. At this time, if a transfer signal inputted to the gate of the transfer transistor 29 makes the transistor 29 turned on, a signal level is transmitted to a floating node 25.
In addition to this state, if the reset transistor 21 is holding a OFF state, a potential level of the floating node 25 which is used as a source terminal of the reset transistor 21 is changed in accordance with the signal charges accumulated in the floating node 25. Therefore, the gate potential of the select transistor 24 is changed.
The change of the gate potential of the select transistor 24 causes the bias of a source terminal of the select transistor 24 to be changed and therefrom the bias of a drain of the access transistor 30 to be changed.
In this case, if a row selection signal is applied to the gate of the access transistor 30 through a row selection signal input terminal 31, then a potential due to the signal charges generated at the photo diode 27 is transmitted to the column selection line 32.
As the result, after a signal level due to the charges generated at the photo diode 27 is detected, a reset transistor 21 is turned into an ON state by the reset signal received through the reset signal input terminal 22 and thereby all the signal charges are reset.
By repeating the aforementioned operations, each signal level as well as a reference potential after the reset operation is read out.
However, the CMOS image sensors in the conventional art still have problems such as follows.
Even though the photo diodes of the CMOS image sensor having a 3 TR pixel structure have a large light receiving region so as to improve a fill factor, an additional circuit is required to remove noises generated in the pixel level and therefore the pixel size is increased.
Furthermore, another serious problem is that the sensitivity is abruptly decreased because of a capacitance of the photo diode directly operating as an input capacitance.
By adopting the CCD technology for the CMOS image sensor of 4 TR pixel structure so as to solve such problem and to control the noise, the quality of the image of the sensor is improved since the charge transmission characteristic is improved. The sensitivity of the sensor adopting the CCD technology is also improved since the floating diffusion node has a low input capacitance. However, because of the use of the photo gate, the blue response characteristic and the fill factor are not so good.
Moreover, there is a possibility that an image lagging phenomenon due to the floating node arises.
Furthermore, the fabricating process is complicated because of forming the photo gate.
Therefore, the present invention is directed to solve these problems of the CMOS image sensors in the conventional art and has one object to provide a CMOS image sensor and a fabrication method for the same.
Therefore, the present invention is directed to solve these problems of the CMOS image sensors in the conventional art and has one object to provide a CMOS image sensor and a fabrication method for the same.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages in accordance with the purpose of the present invention, as embodied and broadly described, the CMOS image sensor according to the present invention comprises a unit cell region having a first region and a second region adjacent to the first region, both regions being defined on a semiconductor substrate; a PDN region (this xe2x80x9cPDN regionxe2x80x9d designates the region to form a photo diode having n type doping on a p type well) having a first PDN region and a second PDN region, the first PDN region being extended from a surface of said first region to a bulk semiconductor in a direction perpendicular to the surface of the semiconductor and a second PDN region being extended from the lower portion of the first PDN region to the lower portion of the second region in a direction perpendicular to the first PDN region; and a floating diffusion region and a reset region, both regions being formed in a surface of the second region above said second PDN region in an accompanying drawing.
A fabrication method of the CMOS image sensor according to the present invention comprises the step of forming an epitaxial layer by epitaxially growing a surface of the semiconductor substrate so as to have a first region and a second region adjacent to the first region; the step of dividing said first and second regions into a plurality of subregions; the step of repeatedly performing a PDN impurity ion doping process once or as many times as the number of said plurality of subregions so as to establish a stepwise potential distribution in said PDN region, the stepwise potential distribution having a stepwise value according to the each position of said subregions; the step of forming transistors for transferring, sensing and resetting image charges generated in said second region; and the step of performing a PDN impurity ion doping process in the first region once more.
The CMOS image sensor in accordance with the present invention has effects as follows.
First, the sensor has an excellent sensitivity characteristic according to the wavelength of light since the PDN region is deeply formed in a depth direction by the ion doping process, as shown in FIG. 6b and FIG. 6c. 
Second, the sensor has a reduced white defect that exists essentially in a photo diode structure since the PDN region is deeply formed.
Third, a light responding characteristic of the sensor is enhanced since a maximum photo diode region in a unit cell region is secured and the fill factor is increased.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.